Field of the Invention
The invention relates to a memory cell configuration in which an electrical resistance of a memory element represents an information item and can be influenced by a magnetic field, and a method for fabricating it.
There are elements whose electrical resistances can be influenced by magnetic fields. These include the so-called giant magnetoresistive (GMR) elements, which have at least two ferromagnetic layers and a nonmagnetic layer disposed in between and exhibit the so-called giant magnetoresistive (GMR) effect. The GMR effect is the term used to denote the fact that an electrical resistance of the GMR element is dependent on whether the magnetizations in the two ferromagnetic layers are oriented parallel or antiparallel to one another. A magnetic field can change the magnetization direction of one or both layers and, consequently, the electrical resistance of the GMR element. In the case of a current flow perpendicular to the planes of the layers of the memory element (i.e. current perpendicular to plane (CPP) configuration), the GMR element has a different electrical resistance and magnetoresistance effect than in the case of a current flow parallel to the planes of the layers of the memory element (current in plane (CIP) configuration) (see the reference by F. W. Patten et al., title xe2x80x9cOverview of the DARPA Non-Volatile Magnetic Memory Programxe2x80x9d, IEEE 1996, pages 1-2).
If the nonmagnetic layer is conductive, then the term referred to is spin valve (SV) effect. If the nonmagnetic layer is insulating, then the term referred to is spin tunneling (ST) or tunneling magnetoresistance (TMR) effect (see Patten et al. loc. cit.).
In order to be able to orient the magnetization directions of the two ferromagnetic layers parallel or antiparallel to one another using a field which permeates both layers, the threshold fields, i.e. the smallest fields which are necessary for changing the magnetization directions, are different for the layers. The magnitude of the threshold fields can be influenced by the choice of materials, by the thickness of the layers, by the size and direction of the magnetic field during the deposition of the layers, and by the temperature during the deposition of the layers (see the reference by J. S. Moodera et al., J. Appl. Phys. 79 (8) 1996, pages 4724 to 4729). Another possibility for influencing the threshold field of a ferromagnetic layer is to dispose, adjoining the ferromagnetic layer, an antiferromagnetic layer which virtually fixes the magnetization direction of the ferromagnetic layer and thus effectively increases the threshold field of the ferromagnetic layer.
The reference by D. D. Tang et al., IEDM 95, pages 997 to 999, and the reference by D. D. Tang et al., IEEE Trans. on Magnetics, Vol. 31, No. 6, 1995, pages 3206 to 3208, propose using GMR elements of this type as memory elements in a memory cell configuration. The magnetization direction of a first ferromagnetic layer of a memory element is fixed by an adjacent antiferromagnetic layer. The magnetization direction of a second ferromagnetic layer can be altered by a magnetic field that is larger than the threshold field of the second layer, without altering the magnetization direction of the first layer. In order that each memory element can be programmed separately, write lines are provided, which cross in the region of the memory elements. In order to program the memory cell, the magnetic field is generated by current being sent through the associated two write lines. The current intensities are dimensioned in such a way that only the superposition of the magnetic fields of both write lines suffices to exceed the minimum intensity required to alter the magnetization direction of the second ferromagnetic layer. The memory elements are connected in series. Each row forms a bit line. The write lines are electrically insulated from the bit lines and the memory elements. In order to read the memory cell, i.e. in order to determine the magnetization direction of its second layer, first a read current is sent through the corresponding bit line and the total voltage dropped across the latter is measured. The two write lines then generate a magnetic field that is larger than the threshold field of the second layer. If the direction of the magnetic field corresponds to the original, i.e. the information-representing magnetization direction of the second layer, then the total voltage on the bit line does not change. Otherwise, the magnetic field changes the magnetization direction of the second layer with the consequence that the total voltage changes.
The reference by S. Tehrani et al., IEDM 96, page 193 et seq., proposes using, as a memory element, a GMR element which has ferromagnetic layers of different thicknesses. The magnetic field for writing in information is dimensioned in such a way that it exceeds the minimum strength for changing the magnetization direction of the thicker of the two ferromagnetic layers. For the read-out, i.e. for the determination of the magnetization direction of the thicker layer, a magnetic field is set which magnetizes the thinner but not the thicker of the two layers in a distinguished direction, and the associated voltage on a bit line is measured. Afterward, a magnetic field is set which magnetizes the thinner layer in the opposite direction and the associated voltage on the bit line is measured. The magnetization direction of the thicker layer is obtained from the sign of the difference between the voltages. The magnetization in the thicker of the two ferromagnetic layers remains uninfluenced by the read-out.
The read-out operation by comparing two successively measured voltages requires an increased outlay on circuitry and takes a long time.
U.S. Pat. No. 5,640,343 describes an MRAM cell configuration in which memory elements are disposed in an x-y grid. First lines run perpendicularly to second lines. The memory elements are each connected between one of the first lines and one of the second lines. For each memory element there are a multiplicity of parallel current paths, which make reliable determination of resistance more difficult.
U.S. Pat. No. 5,173,873 describes an MRAM cell configuration in which a memory element has a magnetoresistive layer disposed between two ferromagnetic layers. The magnetization direction of one of the ferromagnetic layers is changed by an external magnetic field. The other of the ferromagnetic layers has a higher coercive force and its magnetization direction is not altered by the magnetic field. The magnetic field is generated by a line running past the memory element. The sign of the current flow through the line determines whether the information 0 or 1 is written to the memory element. The line is connected to a write line via a transistor that selects the memory element from among other memory elements during writing. In order to write and in order to read out the information, a plurality of transistors and a plurality of lines are provided per memory element, which select the memory element from among other memory elements. This MRAM cell configuration has the disadvantage that because of the many transistors and lines per memory cell, its packing density is low.
It is accordingly an object of the invention to provide a memory cell configuration in which an electrical resistance of a memory element represents an information item and can be influenced by a magnetic field, and a method for fabricating it that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which the information item can be read out with a reduced outlay on circuitry or faster.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration containing a memory cell having a memory element and a transistor connected in series with the memory element. The memory element has an electrical resistance representing an information item that can be influenced by a magnetic field. A write line and a bit line running transversely to the write line and electrically connected to the transistor are provided. The bit line and the write line cross in a region of the memory element and both serve for generating the magnetic field. A gate line is connected to and drives the transistor. The gate line runs transversely with respect to the bit line, and through which the information item can be read out.
The memory cell configuration according to the invention contains the memory cells which each include a memory element, whose electrical resistance represents an information item that can be influenced by a magnetic field, and the single transistor. The transistor allows a selection of the associated memory cell from among the memory cells during the read-out of the information.
Since the transistors enable the selection of the memory cell, it is not necessary to measure two voltages for the purpose of determining the resistance of the memory cell to be read. The other memory cells have no influence on the voltage. This reduces both the reading duration and the outlay on circuitry. The reliability of the resistance measurement is also not adversely affected by large cell arrays.
The memory cells are connected to bit lines. Memory cells adjacent to one another along one of the bit lines are not connected in series with one another. In order to read one of the memory cells, the associated transistor is driven via the gate line running transversely with respect to the bit line, and the resistance of the memory element is determined from the current or the voltage of the associated bit line. Since the memory cells are not connected in series as part of the bit line, only the memory cell to be read influences the current or the voltage of the associated bit line. The remaining memory cells have no influence on the current or the voltage.
In the prior art, the memory cells are often connected in series. The current to be measured does not flow only through the memory cell to be read, for which reason it is reduced by other memory cells. On account of the reduction of the current, a sense amplifier already has to be provided for a small number of series-connected memory cells, which results in a large area requirement.
One advantage of the interconnection proposed in the context of the invention is that the current does not flow through other memory cells and, therefore, is not reduced unnecessarily. Moreover, a particularly high packing density of the memory cell configuration can be achieved since fewer sense amplifiers are required.
Write lines that run transversely with respect to the bit lines and cross the bit lines in regions of the memory elements are provided for the circuit configuration according to the invention. The memory elements can be disposed below, above or between the mutually crossing write lines and bit lines. In order to program a memory cell, a current is sent through the associated write line and a current is sent through the associated bit line. In this case, the currents generate a magnetic field that is stronger in the memory cell than in the remaining memory cells. To ensure that the magnetic field in the memory cell is as large as possible, it is advantageous if the bit line and the write line are disposed as near as possible to the memory element.
A memory cell to be programmed can be selected from among the other memory cells by the mutually crossing write lines and bit lines. In contrast to U.S. Pat. No. 5,173,873, the memory cell does not require a transistor for selection during writing, so that a higher packing density can be realized.
In order to simplify the process and in order to increase the packing density, it is advantageous if gate electrodes of the transistors are parts of the gate lines.
The transistor may be e.g. of a planar configuration. This affords the advantage that it is possible to employ the standard technology for fabricating the transistor. In order to increase the packing density, it is furthermore advantageous if the transistors of adjacent memory cells along the bit line have, in pairs, a common source/drain region.
In order to increase the packing density of the memory cell configuration, the transistor may have a vertical configuration.
The memory cells may be connected to a common voltage terminal. During the reading of the memory cell, the current flows between the voltage terminal and the bit line through the memory cell.
As an alternative, the memory cells may be connected to the write lines in such a way that, during read-out, the current flows between the associated write line and the associated bit line through the memory cell to be read.
In order to reduce the number of lines and, consequently, increase the packing density, it is advantageous if the write line and the gate line coincide. This is possible in particular when the memory cells are connected to the common voltage terminal. Since, in the standard technology, the gate electrodes are produced immediately after the production of gate dielectrics, it is advantageous, for the case where the gate electrodes are parts of the gate lines, if the gate lines are produced first and, in a later process step, the write lines are produced in a manner adjoining the gate lines. In this case, different materials can be used for the write line and for the gate line. As an alternative, the write line and the gate line are produced as a common line in one step.
In order to filter out background noise that is similar for adjacent bit lines, it is advantageous to provide the memory cell configuration with folded bit lines. In the case of folded bit lines, during the reading of the memory cell, the difference between currents or voltages of the corresponding bit line and an adjacent bit line is formed. To ensure that the current or the voltage of the adjacent bit line only represents background noise, it is necessary that the gate line associated with the memory cell not be electrically connected to any memory cell that is electrically connected to the adjacent bit line.
In order to simplify the process, it is advantageous to provide no folded bit lines. The term then referred to is open bit lines.
If the transistor is a vertical transistor, it is possible to produce a semiconductor structure in which a first source/drain region of the transistor is disposed above a channel region. A second source/drain region of the transistor can be disposed below the channel region or offset diagonally downward with respect to the channel region. The gate line is disposed at least on a first side wall of the semiconductor structure.
In order to increase the packing density, it is advantageous if a gate line adjacent to the gate line is disposed on a second sidewall, opposite the first sidewall. In this case, in the region of the channel region, an element which prevents the formation of a channel adjoins the second side wall. This prevents the adjacent gate line from controlling the transistor.
As an alternative, the gate line can be disposed e.g. either on the first sidewall or on the second sidewall.
In order to increase the packing density, the element that prevents the formation of a channel may be e.g. a channel stop region. The channel stop region is doped by the same conductivity type as the channel region but has a higher dopant concentration. The channel stop region may be produced e.g. by inclined implantation or by outdiffusion of dopant from a material.
In order to increase the packing density, the element which prevents the formation of a channel may e.g. also be produced in the form of a preferably spacer-type insulating structure.
In order to produce the semiconductor structure, trenches can be produced in a substrate or in layers disposed above the substrate, as a result of which the semiconductor structure is produced in the form of a strip. The gate lines are produced in the trenches. The semiconductor structure is part of memory cells that are adjacent to one another along the gate line. To ensure that the gate line does not produce any channels between first source/drain regions of the semiconductor structure, further elements that prevent the formation of channels can be disposed between adjacent first source/drain regions.
As an alternative, a semiconductor structure is produced for each memory cell by a lattice-type depression in the form of first trenches and second trenches running transversely with respect to the first trenches being produced in the substrate or in layers disposed above the substrate. As a result of which the semiconductor structure is produced in the form of a parallelepiped. The gate lines are produced in the lattice-type depression, e.g. in and along the first trenches. Between adjacent semiconductor structures along the gate line, insulating structures that prevent the formation of channels can be produced in the lattice-type depression, e.g. in the second trenches.
It is likewise possible also to disposed the gate line in the lattice-type depression between the adjacent semiconductor structures along the gate line. In this case, the gate line surrounds the semiconductor structure in an annular manner. This configuration is advantageous for enlarging the channel width and thus for increasing the current intensity through the transistor. To ensure that semiconductor structures that are adjacent transversely with respect to the gate line can be driven by different gate lines, mutually adjacent gate lines share one of the first trenches. In order to increase the packing density, it is advantageous if parts of the gate lines which are disposed in the first trenches are in spacer form.
If the gate line is only disposed on the first side wall of the semiconductor structure and folded bit lines are provided, then it is advantageous, in order to increase the packing density, if mutually adjacent gate lines are disposed together in one of the trenches. In this case, the elements that prevent the formation of channels alternately adjoin a first sidewall and a second sidewall of the trenches in which the gate lines are disposed. In order to increase the packing density, it is particularly advantageous if the gate lines are in spacer form. If no folded bit lines are provided, it is advantageous, in order to simplify the process, if the gate line fills the trench.
Any element whose electrical resistance can be influenced by a magnetic field is suitable as the memory element. The so-called Lorentz force acts on moving electrons traversing a magnetic field, the force acting perpendicularly to the direction of motion. A layer made of a material in the case of which the Lorentz force causes the electrons to be displaced to one side of the layer can be used as the memory element. In comparison with the electrical resistance of the layer in the absence of a magnetic field, the magnetic field brings about an effective reduction of the layer cross-section perpendicular to the current flow and, accordingly, an increase in the electrical resistance.
A layer made of a material that exhibits the so-called anisotropic magnetoresistance effect may be provided as the memory element. This effect is a property of the material and causes the size of the electrical resistance to depend on whether the magnetic field is present perpendicularly or parallel to the current flow.
It lies within the scope of the invention for the memory element to be a GMR element. It is also possible to use TMR elements.
By way of example, the memory element includes a first magnetic layer, which requires a first threshold field for changing its magnetization direction, and a second magnetic layer, which requires a second threshold field for changing its magnetization direction, the two magnetic layers being separated from one another by a nonmagnetic layer. The nonmagnetic layer may be e.g. a dielectric or conductive. Alternative possibilities for the configuration of the memory element, such as e.g. the configuration of an antiferromagnetic layer for fixing the magnetization direction of one of the magnetic layers, can be found e.g. in the prior art presented in the introductory part of this description. The magnetic layers are ferromagnetic, for example.
The current flow through the memory element may run perpendicularly (CPP configuration) or parallel (CIP configuration) to the planes of the layers of the memory element.
To ensure that the magnetic field that is generated for the purpose of programming does not have to homogeneously permeate the entire memory element, it is advantageous if the dimensions of the magnetic layers are such that each layer includes only one magnetic domain in each case. The magnetization direction is essentially homogeneous within a domain. If the magnetic field permeates most of the layer, then the magnetization direction of the entire domain and thus of the entire layer changes. A further advantage is that the resistance of such a memory element assumes well-defined values. By contrast, if the layer includes a plurality of domains, then the resistance may vary on account of different magnetization directions of the domains. The switching speed of the memory element whose magnetic layers includes only one domain in each case is also greater since the magnetization direction changes as a result of rotation of the magnetization. In the case of a memory element whose magnetic layers include a plurality of domains in each case, the magnetization direction changes both as a result of rotation of the magnetization and as a result of shifting of domain walls.
Suitable materials for the magnetic layers are e.g. Ni, Fe, Co, Cr, Mn, Gd, Dy and alloys thereof, such as NiFe, NiFeCo, CoFe, CoCrFe, and also MuBi, BiFe, CoSm, CoPt, CoMnB, CoFeB. Suitable insulating materials for the nonmagnetic layer are e.g. Al2O3, MgO, NiO, HfO2, TiO2, NbO, SiO2 and DLC (diamond-like carbon). Suitable conductive materials for the nonmagnetic layer are e.g. Cu or Ag.
In order to obtain a sufficiently large threshold field, a material having a high coercive force can be used for the relevant magnetic layer. Deposition of the material in a magnetic field or heat treatment of the deposited material in a magnetic field can likewise bring about a particularly large threshold field.
Preferred magnetization directions can be produced by depositing or heat-treating the magnetic layers in the magnetic field. These methods are based on physical effects, such as crystal anisotropy and uniaxial anisotropy.
The memory element may have more than two magnetic layers that are disposed one above the other and are separated from one another by nonmagnetic layers.
The memory element may be disposed next to the transistor. In order to increase the packing density, it is advantageous if the memory element is disposed above or below the transistor.
If the memory element is disposed above the transistor, a contact may be disposed on the first source/drain region. The write line may be disposed next to the contact, an insulation being disposed on the line. The memory element is produced above the insulation and above and adjoining the contact. The bit line may be produced above the memory element.
It is advantageous if the insulation on the write line is as thin as possible in order that the influence of the write line on the memory element, i.e. the magnetic field generated by the write line at the location of the memory element, is as large as possible. In order to produce the insulation, the contact, in contrast to the write line, can be produced from a hard conductive material. After the production of the contact and the write line, whose upper areas are, for example, initially at the same level, the write line is removed somewhat by chemical mechanical polishing until the contact protrudes somewhat on account of the hardness of the material. The upper areas of the write line and of the contact are now at different levels. In order to produce the insulation, insulating material is deposited and planarized by chemical mechanical polishing until the upper area of the contact is uncovered. The thickness of the insulation depends on the difference between the levels of the upper areas of the write line and of the contact, i.e. it depends on how far the contact projected.
Since the contact adjoins the memory element and the write line should be disposed as close as possible to the memory element, it is advantageous, in order to increase the packing density, if the contact and the write line are disposed as close together as possible. To that end, after the production of the transistor, an insulating layer may be produced, in which the contact is produced. With the aid of a strip-type mask that partly overlaps the contact, the insulating layer is etched selectively with respect to the contact. Afterward, conductive material is deposited and etched back or planarized, as a result of which the write line is produced.
In order to electrically insulate the write line from the contact, it is possible, before the write line is produced, to produce an isolating layer at least on the uncovered areas of the contact. As an alternative, in order to produce the contact, first a contact hole is produced, whose side areas are provided with the isolating layer and which is subsequently filled with the conductive material. The isolating layer is etched selectively with respect to the insulating layer during the production of the write line. This also applies analogously to the bit line if the bit line is disposed below the memory element.
If the intention is for the gate line to coincide with the write line, during the production of the write line, the insulating layer is cut through until the gate line is uncovered.
The contact can also make contact with the memory element from the side instead of from below. This is particularly advantageous for the case where the current flow through the memory element runs parallel to the planes of its layers. If the current flow runs vertically with respect to the planes of the layers of the memory element, then it is possible, if the contact is produced after the memory element, first to produce a contact hole adjoining the memory element. The isolating layer is produced on side areas of the contact hole by deposition and etching-back, the isolating layer extending to a point below the first magnetic layer of the memory element. The contact hole is filled by the deposition of the conductive material. The conductive material is subsequently etched back until a contact is produced, the upper area of which is level with the first magnetic layer. The second magnetic layer is contact-connected by the bit line.
The memory cell configuration can be used, in particular, as an MRAM memory cell configuration.
One possible method of operation is explained below.
In order to program a memory cell, current is sent through the associated write line and through the associated bit line. Depending on the direction of the currents, the magnetization direction of the magnetically softer of the two magnetic layers is set parallel or antiparallel to the magnetization direction of the magnetically harder of the two magnetic layers, whose magnetization direction is not altered.
For read-out, the transistor is driven via the associated gate line and a current is sent through the memory cell, which current is read out on the bit line. The current through or the voltage drop across the memory cell depends on the electrical resistance of the memory element, which in turn depends on the magnetization direction of the softer of the two magnetic layers.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell configuration in which an electrical resistance of a memory element represents an information item and can be influenced by a magnetic field, and a method for fabricating it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.